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Computer organisation and architecture

From Paper 2 (written)
3.15 marks
Describe the fetch stage of the fetch–decode–execute cycle, referring to the registers used.
From Paper 2 (written)
3.24 marks
Explain how clock speed, number of cores and cache size affect processor performance.
From Paper 2 (written)
3.35 marks
    MOV R0, #0    MOV R1, #1loop:    ADD R0, R0, R1    ADD R1, R1, #1    CMP R1, #5    BLT loop    STR R0, 100    HALT
Trace this program (AQA instruction set) and state the value stored in memory location 100. Explain the purpose of the program.
From Paper 2 (written)
3.43 marks
Explain how a processor handles an interrupt.
Score 0 / 17 · 0 of 4 marked

This paper is written by Plasmo in the style of the AQA A-Level Computer Science exam. It is not a past paper and is not produced or endorsed by the exam board.

Computer organisation and architecture Exam Questions: AQA A-Level Computer Science | Plasmo